The present invention relates to the manufacture of integrated circuit semiconductor devices of the type that employ bipolar transistors. In particular, the invention relates to the layout of the collector contacts in NPN transistors.
The reliability of semiconductor devices and integrated circuits is strongly dependent upon the silicon crystal quality and upon the cleanliness of the process. Unwanted impurities, such as copper and sodium, are present in the manufacturing process even under the most stringent conditions of cleanliness. As a result, many popular techniques have been developed to reduce the affect of the unwanted impurities thereby to improve device reliability. The technique of gettering utilizes the phenomenon in which a dopant, particularly phosphorus, can act as a sink for unwanted impurities.
When a very high concentration of phosphorus (N+) is diffused into silicon, diffusion induced lattice defects will be present. There is a great tendency for undesired impurities to fix themselves into those phosphorus contact regions which have lattice damage.
In most instances, the defects do not limit themselves to the diffused regions. Dislocations are usually generated in the area surrounding the diffused regions as the silicon crystal relieves itself of the stress forces. I have found that if the surface of the silicon crystal is chemically etched to reveal the dislocations, the dislocations extend outwardly from the corners of the diffused regions.